Open AccessA low‐power and area‐efficient ultrasound receiver using beamforming successive approximation register analog‐to‐digital converter with capacitive digital‐to‐analog converter combined delay cell structure for 3‐D imaging systems
Author(s) -
Lee Seungah,
Yun Soohyun,
Bae Joonsung
Publication year - 2022
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/ell2.12617
Subject(s) - successive approximation adc , beamforming , electronic engineering , cmos , analog to digital converter , capacitive sensing , capacitor , reduction (mathematics) , capacitance , computer science , electrical engineering , engineering , voltage , physics , mathematics , geometry , electrode , quantum mechanics
The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog‐to‐digital converter (ADC) shares its capacitive digital‐to‐analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power‐hungry ADC buffers. Furthermore, the dual reference 10‐bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.