Open AccessA 4.5 Gb/s/pin transceiver with hybrid inter‐symbol interference and far‐end crosstalk equalization for next‐generation high‐bandwidth memory interface
Author(s) -
Yoon Kungryun,
Park Hyunsu,
Choi Yoonjae,
Sim Jincheol,
Choi Jonghyuck,
Kim Chulwoo
Publication year - 2022
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/ell2.12494
Subject(s) - transceiver , jitter , intersymbol interference , bit error rate , electronic engineering , computer science , transmitter , cmos , demodulation , electrical engineering , engineering , channel (broadcasting) , telecommunications
A 4.5 Gb/s/pin transceiver capable of eliminating the inter‐symbol interference (ISI) and far‐end crosstalk (FEXT) in a hybrid scheme with low power and small area for next‐generation high‐bandwidth memory (HBM) interfaces is presented. Built around the combination of two ISI and FEXT equalization topologies, the transmitter (TX) energy efficiently reduces data‐dependent jitter (DDJ) and crosstalk‐induced jitter (CIJ) by using the compensation signal generated from edge detectors (ED) to ensure the sampling margin. The prototype transceiver, implemented using a 28‐nm complementary metal‐oxide semiconductor (CMOS) process, operates over a 3‐mm mimicked silicon interposer channel with 21.2‐dB loss. It achieves a data rate per density of 9 Gb/s/μm at a bit error rate (BER) < 10 –12 with 0.23 unit interval (UI) eye width for pseudorandom binary sequence (PRBS)15 data while consuming only 1.46 pJ/bit.