Open AccessA fully‐dynamic 6‐bit 3‐bit/cycle SAR ADC with a single differential DAC
Author(s) -
Zhuang Haoyu,
Li Qiang,
Sun Nan
Publication year - 2022
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/ell2.12474
Subject(s) - comparator , successive approximation adc , bit (key) , computer science , power consumption , differential (mechanical device) , electronic engineering , 12 bit , power (physics) , voltage , electrical engineering , cmos , engineering , physics , quantum mechanics , aerospace engineering , computer security
This paper proposes a fully‐dynamic 6‐bit 3‐bit/cycle SAR ADC. Unlike the prior multi‐bit/cycle SAR ADCs that require several differential DACs or consume static power, the proposed SAR ADC needs only one differential DAC and is fully‐dynamic. This helps reduce the circuit complexity, the ADC input capacitance, and the power consumption. Furthermore, its comparator outputs are directly fed back to the DAC array, without any complicated logics, which further reduces complexity. Finally, simulation results demonstrate the effectiveness of the proposed structure.