A three‐stage capacitor‐less low noise LDO regulator for DCO phase noise reduction | Zendy

Jeong Il | Zendy; Lee Junyong | Zendy; Bae Sunghyun | Zendy; Lee Minjae | Zendy

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A three‐stage capacitor‐less low noise LDO regulator for DCO phase noise reduction

Author(s) -

Jeong Il,

Lee Junyong,

Bae Sunghyun,

Lee Minjae

Publication year - 2022

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

eISSN - 1350-911X

pISSN - 0013-5194

DOI - 10.1049/ell2.12447

Subject(s) - low dropout regulator , noise reduction , capacitor , noise (video) , regulator , reduction (mathematics) , phase noise , voltage regulator , stage (stratigraphy) , control theory (sociology) , electronic engineering , materials science , dropout voltage , engineering , computer science , acoustics , electrical engineering , physics , voltage , mathematics , control (management) , chemistry , artificial intelligence , image (mathematics) , biology , paleontology , biochemistry , geometry , gene

A phase noise reduction technique is presented in a three‐stage capacitor‐less (CL) low dropout (LDO) regulator. This paper proposes a simple RC network that reduces the noise from both bias generation and inside the LDO. This LDO is applied to a conventional CMOS LC oscillator and achieved 3 dB reduction of phase noise at 1 MHz offset from 20 GHz output. The line and load regulations are, 90 μV/V and 0.013 μV/mA, and the output noise at 1 MHz is 6.6nV / Hz ${\rm{nV}}/\sqrt {{\rm{Hz}}} $ .

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