Open AccessA fractional‐N MASH2‐k FDC phase‐locked loop architecture enabling higher‐order quantisation noise shaping
Author(s) -
Iwashita Ryoga,
Xu Zule,
Osada Masaru,
Iizuka Tetsuya
Publication year - 2022
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/ell2.12436
Subject(s) - phase locked loop , phase noise , pll multibit , loop (graph theory) , noise (video) , bandwidth (computing) , control theory (sociology) , electronic engineering , noise shaping , computer science , engineering , mathematics , telecommunications , control (management) , combinatorics , artificial intelligence , image (mathematics)
The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability. A MASH2‐k FDC PLL architecture enabling ( k + 2)th‐order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally controlled oscillator is proposed. The linear loop model is derived, and the noise contributions are analysed. The proposed PLL is evaluated with behavioural simulation whose results are consistent with those of the analysis. The results also suggest a lower phase noise of the proposed PLL compared with the conventional one.