Open AccessAn efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices
Author(s) -
Tibenszky Zoltán,
Carta Corrado,
Ellinger Frank
Publication year - 2021
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/ell2.12171
Subject(s) - pmos logic , frequency divider , cmos , electrical engineering , transistor , signal (programming language) , frequency multiplier , voltage divider , current divider , voltage , wilkinson power divider , threshold voltage , electronic circuit , overdrive voltage , optoelectronics , computer science , electronic engineering , physics , engineering , programming language
The idea to use a lower threshold, but slightly slower transistor over the fastest transistor type for large‐signal circuits is presented with experimental verification for a compact divide‐by‐4 true single phase clock (TSPC) frequency divider. The use of the lowest threshold PMOS devices resulted in self‐resonance frequencies of 41.7, 56, and 60 GHz at supply voltages of 0.5, 0.8 and 0.9 V, respectively. Compared to a divider of the same architecture in the same technology, but with higher threshold voltage devices, this corresponds to improvements of 67%, 33% and 27%, respectively. Power consumptions of 26 and 355 μ W were measured for a 20 GHz and a 70 GHz input signal for supply voltages of 0.5 and 0.9 V, respectively. The best knowledge of the authors, these results are the best reported to date for TSPC divider architecture, and they compete with state of the art for inductorless current‐mode logic dividers.