Open AccessHigh‐performance and single event double‐upset‐immune latch design
Author(s) -
Zhang Haineng,
Liu Zhongyang,
Jiang Jianwei,
Xiao Jun,
Zhang Zhengxuan,
Zou Shichang
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2020.1823
Subject(s) - nmos logic , pmos logic , upset , single event upset , transistor , dissipation , soft error , electronic engineering , logic gate , electronic circuit , power (physics) , electrical engineering , computer science , engineering , static random access memory , physics , voltage , mechanical engineering , quantum mechanics , thermodynamics
This Letter proposes a single event double‐upset (SEDU)‐fully‐tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area‐power‐delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.