Open AccessReliability enhanced SiC MOSFET with partially widened retrograde P‐well structure
Author(s) -
Liu Jiawei,
Lu Jiang,
Tian Xiaoli,
Chen Hong,
Bai Yun,
Liu Xinyu
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2020.1627
Subject(s) - mosfet , materials science , power mosfet , reliability (semiconductor) , planar , fabrication , optoelectronics , power semiconductor device , saturation current , threshold voltage , gate oxide , voltage , electrical engineering , electronic engineering , power (physics) , computer science , engineering , transistor , physics , medicine , computer graphics (images) , alternative medicine , quantum mechanics , pathology
In this Letter, a 1.2 kV SiC power MOSFET with a partially widened retrograde P‐well (RP) structure and N ‐implanting region is proposed to enhance the device's reliability. Compared with the conventional SiC power MOSFET, the short circuit (SC) ability of the proposed structure can be improved effectively without sacrificing other performance. Simulation results reveal that a 40% reduction of the SC saturation current can be achieved, resulting in the SC withstand time increase from 7 to 10 μs at the DC‐link voltage 800 V. Moreover, a better gate oxide reliability at 1.2 kV blocking condition also can be achieved. The peak electric field at the gate oxide interface is decreased by ∼48% owing to the shielding effect of the RP structure. In addition, the fabrication technology of the proposed structure is compatible with the standard planar SiC MOSFET manufacture process only with a few additional implanting steps. Therefore, this new MOSFET structure provides a simple and effective way to optimise the reliability of the planar SiC power MOSFET.