Open AccessGate leakage compensation technique for self‐cascode based voltage references
Author(s) -
Olivera F.,
Petraglia A.
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2020.1452
Subject(s) - cascode , leakage (economics) , cmos , materials science , transistor , voltage , electrical engineering , compensation (psychology) , threshold voltage , optoelectronics , electronic engineering , silicon on insulator , silicon , computer science , topology (electrical circuits) , engineering , psychology , psychoanalysis , economics , macroeconomics
This communication describes a gate leakage compensation technique to ensure wide‐temperature operation and wide‐supply regulation of traditional self‐cascode based voltage references in deep nanometre nodes ( < 65nm ). Extensive simulations in 28 nm ultra‐thin buried oxide fully depleted silicon‐on‐insulator CMOS process show that the proposed 4‐transistor topology can operate down to 0.2 V, generating a reference voltage of 98.2 mV with mean and best temperature coefficients of 68.9 and 18.2ppm / ° C , respectively, from − 40 to 120° C .