Gate leakage compensation technique for self‐cascode based voltage references

This communication describes a gate leakage compensation technique to ensure wide‐temperature operation and wide‐supply regulation of traditional self‐cascode based voltage references in deep nanometre nodes ( < 65nm ). Extensive simulations in 28 nm ultra‐thin buried oxide fully depleted silicon‐on‐insulator CMOS process show that the proposed 4‐transistor topology can operate down to 0.2 V, generating a reference voltage of 98.2 mV with mean and best temperature coefficients of 68.9 and 18.2ppm / ° C , respectively, from − 40 to 120° C .