Open AccessError‐compensated time integrator in 28‐nm CMOS technology
Author(s) -
Ji Xincun,
Wang Youhua,
Shen Mengqi,
Guo Yufeng
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2020.1074
Subject(s) - integrator , adder , cmos , offset (computer science) , electronic engineering , integrating adc , sampling time , computer science , voltage , electrical engineering , control theory (sociology) , engineering , mathematics , capacitor , statistics , control (management) , artificial intelligence , ćuk converter , programming language
A time‐difference integrator is proposed to compensate for the time error caused by leakage current in gated delay‐buffer cells. The proposed time integrator, consisting of two back‐to‐back connected time‐difference adders, which are composed of two gated delay‐buffer cells. The input time signals and accumulated output are periodically swapped into the time adder to neutralise the timing offset. Implemented in a 28‐nm CMOS process, the time integrator achieves a gain of 27.39 dB with a 317 kHz 30 ps peak‐to‐peak sinusoidal input, and consumes 110.3 μW with a 50 MHz sampling rate from a 0.9 V supply.