Open AccessDither‐based calibration of bit weights in pipelined‐SAR ADCs with fast convergence speed using partially split structure
Author(s) -
Sun Jie,
Li Xin,
Yan Chenggang,
Liu Weiqiang
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2020.0579
Subject(s) - dither , calibration , converters , spurious free dynamic range , signal (programming language) , distortion (music) , convergence (economics) , computer science , shaping , algorithm , signal to noise ratio (imaging) , dynamic range , interference (communication) , spurious relationship , noise (video) , electronic engineering , bit (key) , mathematics , cmos , noise shaping , telecommunications , physics , engineering , artificial intelligence , voltage , channel (broadcasting) , economic growth , amplifier , quantum mechanics , machine learning , programming language , statistics , economics , computer security , image (mathematics)
A background calibration technique is proposed to correct bit weights in pipelined‐successive‐approximation‐register (SAR) analogue‐to‐digital converters (ADCs). By splitting the second stage, the input signal interference is mostly removed, thereby greatly enhancing the convergence speed of the algorithm. Besides, the dither signal assists to eliminate mismatch issues between the partially split ADCs, thus relaxing the analogue overheads. According to the simulation, after calibration, the spurious‐free‐dynamic‐range and signal‐to‐noise‐and‐distortion‐ratio are improved from 53.2 to 88.2 dB and 49.5 to 75.2 dB, respectively. The calibration algorithm converges with about only 600 K samples.