Open AccessBackground calibration of bit weights in pipeline ADCs using a counteracting dither technique
Author(s) -
Sun Jie,
Zhou Yuan,
Li Xin
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2020.0006
Subject(s) - dither , comparator , spurious free dynamic range , capacitor , electronic engineering , pipeline (software) , converters , computer science , spurious relationship , weighting , dynamic range , noise shaping , engineering , electrical engineering , voltage , physics , machine learning , programming language , acoustics
A counteracting dither technique is proposed to remedy the bit‐weight error issue in pipeline analogue‐to‐digital converters (ADCs). A capacitor is added to the traditional comparator dither scheme. By switching the added capacitor, the residue swing increment due to comparator dither is counteracted, thereby greatly relaxing the design requirement of the residue amplifier. Behaviour‐level simulation results show that the spurious‐free‐dynamic‐range and the signal‐to‐noise‐and‐distortion‐ratio are improved from 59 and 52.8 dB to 102.7 and 85 dB after calibration in a 14‐bit ADC, respectively.