22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time‐to‐digital converter in CMOS 65 nm for single photon avalanche diode array | Zendy

Nolet F. | Zendy; Roy N. | Zendy; Carrier S. | Zendy; Bouchard J. | Zendy; Fontaine R. | Zendy; Charlebois S.A. | Zendy; Pratte J.F. | Zendy

Open Access

22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time‐to‐digital converter in CMOS 65 nm for single photon avalanche diode array

Author(s) -

Nolet F.,

Roy N.,

Carrier S.,

Bouchard J.,

Fontaine R.,

Charlebois S.A.,

Pratte J.F.

Publication year - 2020

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

ISSN - 1350-911X

DOI - 10.1049/el.2019.4105

Subject(s) - jitter , vernier scale , time to digital converter , cmos , ring oscillator , differential nonlinearity , diode , single photon avalanche diode , physics , materials science , detector , electronic engineering , electrical engineering , optics , avalanche photodiode , optoelectronics , engineering , clock signal

A Vernier ring‐oscillator‐based time‐to‐digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of 0.00151mm 2 . Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to 22μ W at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors.

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