Open Access80 GS/s 5.5 ENOB time‐interleaved inverter‐based CMOS track‐and‐hold
Author(s) -
Mattia O.E.,
Murmann B.
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.4104
Subject(s) - effective number of bits , cmos , inverter , electrical engineering , electronic engineering , computer science , engineering , voltage
An inverter‐based track‐and‐hold circuit that merges the functions of buffering and sampling is proposed, simultaneously improving linearity, bandwidth and power efficiency when compared to state‐of‐the‐art designs. The circuit operation and its governing equations are presented, and simulation results of an 80 GS/s, 5.5 ENOB time‐interleaved prototype consuming 25 mW from a 0.7 V supply demonstrate the advantages of the proposed topology using a predictive 7 nm FinFET CMOS technology.