Open AccessDemodulation type single‐phase PLL with DC offset rejection
Author(s) -
Ahmed H.,
Benbouzid M.
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.3718
Subject(s) - phase locked loop , demodulation , offset (computer science) , electronic engineering , pll multibit , computer science , phase (matter) , dc bias , control theory (sociology) , electrical engineering , physics , engineering , phase noise , telecommunications , voltage , channel (broadcasting) , control (management) , artificial intelligence , programming language , quantum mechanics
This Letter proposes demodulation type PLL for phase and frequency estimation of single‐phase system that can reject DC offset. Using results from the adaptive estimation literature, this Letter proposes a linear parametric model‐based initial phase angle estimation approach. Then by using differentiation and integration operation on the estimated initial phase angle, the frequency is estimated. This avoids the use of any low‐pass filter unlike conventional demodulation‐based technique. Moreover, unlike existing demodulation‐based technique, the proposed technique can completely reject DC offset. Comparative experimental results, provided with state‐of‐the‐art DC offset rejection‐based enhanced phase locked‐loop, clearly demonstrate the suitability of the proposed technique.