Open AccessReferenceless single‐loop CDR with a half‐rate linear PD and frequency acquisition technique
Author(s) -
Kim H.R.,
Chun J.H.
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.3075
Subject(s) - jitter , detector , phase detector , phase locked loop , physics , phase frequency detector , electronic engineering , control theory (sociology) , computer science , optics , engineering , voltage , charge pump , control (management) , quantum mechanics , artificial intelligence , capacitor
A referenceless single‐loop clock and data recovery (CDR) circuit with a half‐rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle‐slip in the half‐rate linear PD and its relationship with the frequency acquisition are described in detail. The single‐loop CDR consists of a conventional phase‐tracking loop and a frequency‐tracking unit, referred to as the cycle‐slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak‐to‐peak jitter of the recovered clock are 2.40ps rmsand 21.4ps pp , respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as 0.3UI pp . The CDR occupies 0.105mm 2and consumes 26 mW at 8 Gb/s from a 1.0 V supply.