Open AccessUniform shallow trenches termination design for high‐voltage VDMOS transistor
Author(s) -
Li Qi,
Bao Tingting,
Li Haiou,
Sun Tangyou,
Zuo Yuan
Publication year - 2020
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.2982
Subject(s) - electric field , transistor , breakdown voltage , voltage , curvature , electrical engineering , enhanced data rates for gsm evolution , materials science , fabrication , field effect transistor , optoelectronics , engineering , high voltage , physics , geometry , telecommunications , medicine , mathematics , alternative medicine , pathology , quantum mechanics
A new uniform shallow trenches termination (ST 2 ) with field plate for high‐voltage VDMOS transistor is proposed in this Letter. In ST 2 structure, the electric field near the source is decreased and the depletion region is extended by the field plate, besides, many electric field peaks are introduced in shallow trenches under the field plate and the average electric field strength is increased, both improve the characteristic of the breakdown voltage (BV). Simulation results show the BV of ST 2 VDMOS is 706 V with a termination length L d = 132 μm, which reaches 97% of that of the parallel‐plane junction, and the influence of the edge curvature effect is almost entirely eliminated. The ST 2 structure is compatible with conventional CMOS process with only one additional mask and its fabrication is low‐cost.