Open Access12 Gbit/s three‐tap FFE half‐rate transmitter with low jitter clock buffering scheme
Author(s) -
Park K.,
Oh T.
Publication year - 2019
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.2226
Subject(s) - jitter , transmitter , gigabit , signal (programming language) , clock signal , cmos , electronic engineering , computer science , electrical engineering , engineering , channel (broadcasting) , programming language
A 12 Gbit/s feed‐forward equalisation (FFE) transmitter has been designed in 65 nm CMOS process. The three‐tap/half‐rate high‐speed tap signal generation technique for the segmented FFE driver is presented. A clock buffer scheme to make the equivalent signal transition for each segmented unit contributes to a low jitter performance. The measurement results show 9.31 ps RMS jitter at 12 Gbit/s after equalisation and the horizontal eye‐opening is 0.204 UI at 10 − 12BER. The prototype transmitter occupies 0.042mm 2 and consumes 1.58 pJ/bit.