Open Access8.4‐to‐16‐bit resolution, 1‐to‐16 kHz bandwidth ADC with programmable‐gain functionality for multi‐sensor applications
Author(s) -
Rhee C.,
Kim S.
Publication year - 2019
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.1496
Subject(s) - delta sigma modulation , bandwidth (computing) , electronic engineering , successive approximation adc , adder , cmos , computer science , noise shaping , electrical engineering , engineering , voltage , telecommunications , capacitor
A resolution‐reconfigurable, bandwidth‐scalable analogue‐to‐digital converter (ADC) with programmable‐gain (PG) functionality for a multi‐sensor system, which encompasses various signals such as bio‐signals and battery‐level, is presented. In PG and low‐power mode, a PG first‐order noise‐shaping (NS) successive‐approximation register (SAR) ADC achieves 8.4‐to‐10.2‐bit operating up to 16 kHz while providing a gain of 1/2/4. The PG NS SAR ADC can be reconfigured as an adder and a quantiser in a delta‐sigma (ΔΣ) modulator enhancing the order of the modulator for high‐resolution. The third‐order ΔΣ modulator achieves 16.1 bits in a bandwidth of 1 kHz. The work is implemented in a 0.18 μm CMOS process with a 1.8 V power supply.