Open AccessDither‐based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs
Author(s) -
Wang Peng,
Sun Jie,
Wu Jianhui
Publication year - 2019
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.0872
Subject(s) - dither , noise (video) , shaping , register (sociolinguistics) , calibration , capacitor , computer science , electronic engineering , mathematics , noise shaping , artificial intelligence , electrical engineering , statistics , engineering , voltage , image (mathematics) , linguistics , philosophy
A dither‐based background calibration with data‐weighted averaging logic to correct capacitor mismatch and inter‐stage gain error in pipelined noise shaping successive approximation register ADCs is proposed. By injecting the dither signal in the background, the inter‐stage gain is obtained. Besides, the data‐weighted averaging logic is adopted to dissipate harmonics caused by the mismatch of capacitors. Owing to the effective combination of the two methods, there is no need to detect the conditions of injecting the dither signal. As a result, the calibration requires simple logic and adds little analogue overhead.