Open AccessOscillator without a combinatorial loop and its threat to FPGA in data centre
Author(s) -
Sugawara T.,
Sakiyama K.,
Nashimoto S.,
Suzuki D.,
Nagatsuka T.
Publication year - 2019
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2019.0163
Subject(s) - field programmable gate array , loop (graph theory) , computer science , gate array , isolation (microbiology) , ring oscillator , embedded system , domain (mathematical analysis) , computer hardware , mathematics , engineering , electronic engineering , mathematical analysis , combinatorics , microbiology and biotechnology , biology , cmos
Virtual field‐programmable gate array (FPGA) is an emerging technology to put multiple users in the same FPGA fabric with logical isolation. Security researchers have studied new threats in virtual FPGA and proposed attacks on the logical isolation by exploiting analogue natures of FPGA. These attacks use an oscillator comprising a combinatorial loop to have access to the analogue domain using digital components only. Interestingly, the system in the field prohibits a combinatorial loop by a design rule check. In this Letter, the authors study if prohibiting a combinatorial loop is sufficient to thwart the conventional attacks. They negatively answer the question by showing oscillators without a combinatorial loop. They also show how to detect and reject the proposed oscillators by a design rule check.