Open AccessHistogram‐based mixed‐signal time‐to‐digital‐converter array for direct time‐of‐flight depth sensors
Author(s) -
Seo H.,
Choi J.
Publication year - 2019
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2018.7914
Subject(s) - differential nonlinearity , histogram , chip , least significant bit , computer science , cmos , signal (programming language) , integral nonlinearity , sampling (signal processing) , electronic engineering , detector , engineering , artificial intelligence , electrical engineering , voltage , telecommunications , converters , programming language , operating system , image (mathematics)
This Letter introduces a histogram‐based time‐to‐digital‐converter (TDC) array for direct time‐of‐flight depth sensors. The 12‐bit TDC array measures the time of flight (TOF) of a light pulse that is detected using an external single‐photon avalanche diode (SPAD) array. As SPADs are noisy owing to dark electrons and scattered photons, statistical measurements based on histograms are essential, but require a large memory. In this work, the authors propose a mixed‐signal TDC with an integrated histogram generation unit (HGU) that reduces memory requirement significantly as well as filters out invalid TOF readings. In addition, for application of the high‐resolution SPAD array, an area‐efficient TDC array with high uniformity was implemented by the proposed phase‐dependent latching and temporal double sampling schemes. The prototype chip was fabricated using a 180 nm CMOS process, including 8‐channel TDCs. The measurements show an integral non‐linearity (INL)/a differential nonlinearity (DNL) of 0.76/0.49 least significant bit (LSB) and high uniformity under 0.19 LSB. The HGU was designed off‐chip for prior verification, and was post‐simulated with the measured TOF from the fabricated chip. Using the histogram‐based TDC, the authors could detect an object located at a distance of 3 m accurately while reducing memory requirement by more than 128 times.