Open AccessDesign of highly reliable energy‐efficient SEU tolerant 10T SRAM cell
Author(s) -
Kumar C.I.,
Anand B.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2018.7267
Subject(s) - static random access memory , voltage , computer science , electronic engineering , noise margin , transistor , electrical engineering , engineering
A novel energy‐efficient radiation hardened by design 10T static RAM (SRAM) cell is proposed. The parasitic extracted simulations show that by employing the proposed 10T‐SRAM cell, an average improvement of ∼ 29, 5/10%, and 108/129%, in layout area, write/read access time (WAT/RAT), and write/read static noise margin (WSNM/RSNM), respectively, is obtained over the recently reported 10T‐SRAM cell at a supply voltage 0.4 V in STMicroelectronics 65 nm technology. The proposed SRAM cell at 32 nm technology node using technology computer‐aided design mixed‐mode simulations is also validated. In 32 nm technology, the proposed SRAM cell shows 42/125% and 54/8%, in WSNM/RSNM and WAT/RAT, respectively, better results as compared with 10T SRAM cell at a supply voltage 0.3 V. In 32 nm technology, the proposed SRAM cell can mitigate the impact of heavy‐ion strike with a linear energy transfer of 30 MeV cm 2 /mg.