Open AccessCapacitor mismatch calibration method for SAR ADC with minimum area and power penalty
Author(s) -
Yang Xiaolin,
Zhao Menglian,
Wu Xiaobo
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2018.6437
Subject(s) - capacitor , successive approximation adc , calibration , spurious free dynamic range , electronic engineering , power (physics) , cmos , distortion (music) , dynamic range , voltage , computer science , electrical engineering , mathematics , engineering , physics , amplifier , statistics , quantum mechanics
A novel capacitor mismatch calibration method is presented to compensate the capacitor mismatches in a successive approximation register (SAR) ADC. The method features a new weight‐balancing split capacitive DAC which allows automatic extraction and calibration of the capacitor mismatches by itself. As a result, the ADC's resolution can be substantially improved with minimum area and power penalty. The calibration method was verified and implemented in a 14 bit, 10 kS/s SAR ADC, fabricated in a 0.13 µm standard CMOS process. The measured signal‐to‐noise‐plus‐distortion and spurious‐free dynamic range are 72.7 and 86 dB after calibration with 13.6 and 21.8 dB improvements, respectively. The total power consumption is 15.2 µW at a 1.2 V supply voltage.