Highly digital 1 GS/s 7‐bit PWM ADC in 65 nm CMOS using time‐domain quantisation | Zendy

Saha A. | Zendy; Harjani R. | Zendy

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Highly digital 1 GS/s 7‐bit PWM ADC in 65 nm CMOS using time‐domain quantisation

Author(s) -

Saha A.,

Harjani R.

Publication year - 2018

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

eISSN - 1350-911X

pISSN - 0013-5194

DOI - 10.1049/el.2018.5393

Subject(s) - cmos , successive approximation adc , bit (key) , electronic engineering , time domain , computer science , pulse width modulation , physics , electrical engineering , engineering , voltage , capacitor , computer vision , computer security

A 2 × time‐interleaved 1 GS/s 7b ADC is presented, which uses pulse‐width modulation and time domain quantisation for digitisation and is designed for wide channel bandwidths available at mm‐wave frequencies. The area, resolution and power performance of the highly digital time‐domain architecture is likely to scale with technology. The prototype ADC achieves 5.24 ENOB at a Nyquist rate while consuming 5.22 mW of power, resulting in a FOMWalden , nyq= 138.13 fJ/conversion step in TSMC's 65 nm GP CMOS process.

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