Open AccessWide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop
Author(s) -
Ramaswami Palaniappan A.,
Siek L.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2018.1134
Subject(s) - flip flop , electrical engineering , sense amplifier , capacitance , low voltage , amplifier , voltage , sense (electronics) , transistor , electronic engineering , computer science , buffer amplifier , cmos , engineering , physics , electrode , quantum mechanics
A new wide‐input dynamic range flip‐flop capable of operation at an ultra‐low supply voltage of 0.16 V is presented. The proposed flip‐flop named as capacitively boosted sense‐amplifier flip‐flop (CB‐SAFF) utilises a capacitively boosted sense‐amplifier master stage to sense the data signals and amplify them to a voltage higher than the supply and below the ground for driving the slave latch stage with improved strength. Using the same size of input/output transistors and load capacitance, the proposed CB‐SAFF outperforms existing state‐of‐the‐art sense‐amplifier flip‐flop designs at a low supply voltage operation from 0.16 to 0.6 V in terms of power delay product and clock to output propagation delay performance metrics. In addition, the proposed CB‐SAFF can also sample low‐swing data signals down to 0.2 V even at a 0.16 V supply voltage and 1 MHz clock frequency, thus making it highly suitable for applications that demand high speed and low power consumption such as for use in ultra‐low voltage Internet of Things, wireless sensor nodes and smart motes.