Open AccessAutonomous high‐speed serial link power management depending on required link performance for HMC
Author(s) -
Jeon D.I.,
Chung K.S.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2018.0997
Subject(s) - dram , computer science , link (geometry) , power management , power (physics) , overhead (engineering) , power consumption , dynamic demand , power saving , electronic engineering , embedded system , computer hardware , engineering , computer network , physics , quantum mechanics , operating system
Many studies on 3D‐stacked dynamic RAMs (DRAMs) have been conducted to overcome the shortcomings of conventional DRAM. The hybrid memory cube (HMC) is one of the most promising 3D‐stacked DRAMs, thanks to its high bandwidth and expandable structure. However, a high‐speed serial link that interfaces the CPU and HMC consumes significant power, primarily because of the high overhead incurred in synchronising its clock. Although the link provides low‐power modes, managing them is very difficult because of their long mode transition times. An autonomous power management method for the high‐speed link is proposed. The proposed method determines the optimal number of active links while satisfying the required link performance. Simulations demonstrate that the proposed method reduces link power consumption by an average of 63.06% with a performance degradation of only 1.36%. Therefore, this proposed autonomous link power management is an outstanding option for low‐power HMC‐based systems.