Open Access0.5–4.4 Gbit/s PAM4/NRZ dual‐mode transceiver with 0.6 V near‐ground NMOS driver for low‐power memory interface
Author(s) -
Min K.,
Oh T.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2018.0871
Subject(s) - transceiver , cmos , nmos logic , power (physics) , gigabit , electronic engineering , electrical engineering , interface (matter) , voltage , channel (broadcasting) , computer science , chip , engineering , transistor , physics , quantum mechanics , maximum bubble pressure method , bubble , parallel computing
An efficient dual‐mode input and output transceiver scheme is proposed. The transceiver can achieve the data speed from 0.5 up to 4.4 Gbit/s with 0.6 V supply voltage and can support the near‐ground mode for low‐power memory interface application. The transceiver can transmit both PAM4/NRZ signals flexibly depending on the channel loss conditions. The prototype bi‐directional two‐channel transceiver is implemented in 45 nm CMOS process and occupies 0.0516 mm 2 chip area. The IP shows power consumption of 2.24/2.78 mW during 4.4 Gbit/s PAM4/NRZ mode operation, each, respectively.