Open Access10 GHz highly linear up‐conversion mixer in 65 nm CMOS
Author(s) -
Li J.,
Gu Q.J.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2018.0780
Subject(s) - cmos , materials science , optoelectronics , electrical engineering , electronic engineering , engineering
A highly linear folded‐type up‐conversion mixer working at 10 GHz is presented. The mixer utilises a feedback loop to linearise the g m stage and make the effective g m only determined by a resistor theoretically. Moreover, the effects of local oscillator (LO) power levels on the circuit DC condition and linearity performances are examined from both the theoretical analysis and measurement results. The mixer prototype, fabricated in a 65 nm CMOS technology, consumes 7.7 mW from 1.2 V supply voltage and exhibits 13.4 dBm OIP3 at the LO power of 2 dBm.