Open AccessNMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits
Author(s) -
Shah A.P.,
Yadav N.,
Beohar A.,
Vishvakarma S.K.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2018.0546
Subject(s) - nmos logic , schmitt trigger , negative bias temperature instability , electrical engineering , electronic circuit , cmos , inverter , transistor , electronic engineering , voltage , computer science , mosfet , engineering
A novel N‐type MOS (NMOS) only Schmitt trigger with voltage booster (NST‐VB) circuit is presented. The proposed NST‐VB circuit uses NMOS transistors in both pull‐up and pull‐down networks to reduce the effect of negative bias temperature instability (NBTI) on the circuit. The proposed circuit is less affected by both inter‐die and intra‐die process variations in consequence of NMOS only structure. Owing to NBTI, the increase in delay for the proposed NST‐VB circuit is only 0.47% as compared with 7.2% for conventional Schmitt trigger after the stress time of three years. For the viability of the proposed circuit figure of merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.35 × and 3.53 × improved FOM as compared with the conventional Schmitt trigger and NMOS inverter, respectively.