Open AccessDesign of optimised logic interface for network‐on‐chip architectures
Author(s) -
Sakthivel E.,
Arunraja M.,
Uma K.D.,
Shanthi T.,
Muthukrishnan A.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2018.0302
Subject(s) - computer science , scalability , chip , embedded system , energy consumption , computer hardware , electronic engineering , real time computing , engineering , electrical engineering , telecommunications , database
Achievement of low power consumption in the field of network‐on‐chip (NoC) is a prominent research in recent days. Many works have attempted to improve performance in NoC using architectural and algorithmic models. The researches attempted to mitigate certain factors like power consumption, speed, complexity, scalability, and flexibility. Currently, NoC engineers incorporated external or internal sense amplifier (SA) in the architectural model of NoC. In the conventional double‐tail SAs (DTSAs), more amount of energy is consumed in the heavy traffic state. Hence, many improved DTSAs like reconfigurable DTSA (R‐DTSA), variable energy aware SA link for asynchronous NoC (VELAN) DTSA (V‐DTSA) were proposed in the previous works and employed with the transceivers. They were evaluated on TSMC 90 nm technology with the real‐time data traffics which are obtained using traffic estimators and traffic generators. An optimised logic interface for transceivers of NoC which is superior to the conventional DTSA, R‐DTSA, and V‐DTSA is developed. The proposed design is implemented with transceivers and evaluated on TSMC 90 nm technology for comparing the performance with the previous SAs.