Open AccessEnergy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
Author(s) -
Villemur M.,
Julian P.,
Andreou A. G.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2017.4738
Subject(s) - simd , computer science , cmos , chip , dissipation , voltage , computer hardware , energy (signal processing) , efficient energy use , architecture , binary number , embedded system , computer architecture , electronic engineering , electrical engineering , parallel computing , engineering , telecommunications , physics , art , statistics , mathematics , arithmetic , visual arts , thermodynamics
This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece‐wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight‐neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low‐voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V.