Open AccessAdvanced layout techniques for high‐speed analogue circuits in 28 nm HKMG CMOS process
Author(s) -
Meng F.,
Li K.,
Thomson D.J.,
Wilson P.,
Reed G.T.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2017.4453
Subject(s) - cmos , electronic circuit , figure of merit , benchmark (surveying) , transistor , process (computing) , materials science , electronic engineering , logic gate , integrated circuit , optoelectronics , computer science , electrical engineering , engineering , geodesy , voltage , geography , operating system
The effect of optimising the transistor finger width on the performance of high‐speed analogue circuits in deep sub‐micron processes is investigated, demonstrated in a 28 nm high‐K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used.