Open AccessOpen‐loop per‐pin skew compensation with lock fault detector for parallel NAND flash memory interface
Author(s) -
Kang K.T.,
Kim S.Y.,
Lee K.Y.
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.4341
Subject(s) - skew , lock (firearm) , fault detection and isolation , compensation (psychology) , computer science , fault (geology) , delay locked loop , cmos , loop (graph theory) , calibration , detector , voltage , electronic engineering , phase locked loop , control theory (sociology) , electrical engineering , engineering , physics , jitter , mathematics , psychoanalysis , actuator , psychology , telecommunications , mechanical engineering , combinatorics , seismology , geology , artificial intelligence , control (management) , quantum mechanics
An open‐loop per‐pin skew compensation with lock fault detection is presented. The proposed circuit employs an open‐loop reference selector, a two‐stage open‐loop delay lock method which is separated by a coarse and fine lock for fast lock‐in time, and a fault lock detecting scheme to prevent lock fault by dead zone of samplers. A unidirectional scan method ahead the fine lock stage to minimise pin‐to‐pin skew errors after calibration is also applied. The circuit was fabricated with 55 nm CMOS technology with a 1 V supply voltage and an area of 0.0036 mm 2 for one de‐skewing module. The measured result shows that the skew error at 1 GHz operation was reduced to <6 ps after skew calibration when the skew between input/output (IO) pins was 230 ps, and the lock‐in time was 11 clock cycles.