0.75 V 2.6 GHz digital bang–bang PLL with dynamic double‐tail phase detector and supply‐noise‐tolerant g m ‐controlled DCO

A compact low‐supply‐voltage yet low‐noise digital bang–bang PLL (DBBPLL) is proposed. The bang–bang phase detector is based on a dynamic double‐tail latch which enables high time‐to‐voltage gain and low input‐referred noise under tight power‐supply headroom. The ring‐based digitally controlled oscillator (DCO) is made of multiple g m ‐controlled delay units and a constant‐ g m ‐biased current DAC. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in a mainstream 28 nm CMOS process with a compact die area of 0.014 mm 2 . When operating at 2.6 GHz, it consumes 2.9 mW with 0.75 V supply and achieves low in‐band phase noise of −105 dBc/Hz.