Open Access160 MS/s 20 MHz bandwidth third‐order noise shaping SAR ADC
Author(s) -
Ghaedrahmati Hanie,
Zhou Jianjun
Publication year - 2018
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2017.3969
Subject(s) - oversampling , noise shaping , comparator , successive approximation adc , electronic engineering , bandwidth (computing) , noise (video) , computer science , capacitor , electrical engineering , settling time , effective number of bits , cmos , engineering , telecommunications , voltage , artificial intelligence , image (mathematics) , control engineering , step response
This Letter proposes an operational‐amplifier free with an embedded passive gain technique to implement an oversampling, noise shaping successive approximation register (SAR) ADCs. In the proposed scheme, the comparator noise, quantisation noise, settling errors and DAC thermal noise are alleviated. A third‐order noise shaping SAR ADC with inserted passive gain design in 40 nm CMOS technology is well suited for low power application because of using passive elements like capacitors and switches. Due to the oversampling and shaping scheme, the structure can be used for high‐speed and high‐resolution operation.