Open AccessFive to 25 Gb/s continuous time linear equaliser with transversal architecture
Author(s) -
Zhang H.,
Monaco E.,
Bassi M.,
Mazzanti A.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.3120
Subject(s) - equaliser , transversal (combinatorics) , channel (broadcasting) , bit error rate , electronic engineering , mathematics , control theory (sociology) , engineering , computer science , electrical engineering , mathematical analysis , control (management) , artificial intelligence
Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with high accuracy in matching the channel response. A continuous time linear equaliser (CTLE) with a transversal architecture features variable DC gain and two zeros that can be tuned independently. The transversal architecture yields a paraboloid mean‐square‐error surface, allowing optimal adaptation through gradient descent algorithms. The CTLE was realised in a 28 nm CMOS technology and measurements are presented at data rate from 5 to 25 Gb/s across 20 dB‐loss channels. Core power dissipation is 17 mW from 1 V supply and horizontal eye opening at BER 10 −12 is equal or larger than 50%, comparing favourably against previously reported equalisers targeting similar data‐rate and channel loss.