Open Access2 × 3.2 Gb/s single‐ended IO transmitter with low‐power dynamic FIR driver for the LPDDR4 standard
Author(s) -
Kim S.,
Oh T.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.2768
Subject(s) - transmitter , cmos , power (physics) , weighting , electrical engineering , electronic engineering , dynamic range , computer science , engineering , physics , acoustics , channel (broadcasting) , quantum mechanics
A novel FIR driver that can be applied to a low power mode in the (Low Power Double Data Rate 4) LPDDR4 standard has been developed. The proto‐type transmitter architecture is implemented in 45 nm CMOS process and occupies 0.009 mm 2 area. The pre‐emphasis tap weighting improves the eye opening by 27.9% vertically and 27% horizontally, respectively, and the transmitter consumes only 2.25 mW at 3.2 Gb/s.