Open AccessHardware‐efficient multi‐channel digital sigma‐delta modulator
Author(s) -
Cho J.K.,
Jeong M.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2017.2483
Subject(s) - integrator , delta sigma modulation , electronic engineering , computer science , noise (video) , multiplexing , computer hardware , channel (broadcasting) , noise margin , modulation (music) , signal to noise ratio (imaging) , engineering , electrical engineering , cmos , telecommunications , voltage , physics , bandwidth (computing) , artificial intelligence , acoustics , image (mathematics) , transistor
A method for implementing a hardware‐efficient multi‐channel digital sigma‐delta modulator is presented for processing field sequential multiple inputs. Compared to a conventional one, which processes the inputs in a time‐multiplexed manner without sharing integrator memory for the multiple sequential inputs, the proposed method significantly reduces the number of storage bits in the integrator memory by partially sharing the integrator memory for the inputs. Simulation results on modulator noise power spectral density and overall signal‐to‐noise ratio match well with those based on quantitative noise analysis.