Open AccessMatrix phase detector for high bandwidth and low jitter frequency synthesis
Author(s) -
Tajalli A.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.1747
Subject(s) - jitter , phase locked loop , bandwidth (computing) , phase detector , phase noise , pll multibit , cmos , detector , electronic engineering , comparator , phase frequency detector , computer science , physics , electrical engineering , engineering , telecommunications , charge pump , voltage , capacitor
A phase‐locked loop (PLL) architecture based on a 2D phase comparator matrix is introduced. In its general form, multiple phases of the input reference clock are compared with multiple phases of the feedback clock, allowing for wider bandwidth (BW) and lower phase noise generation of the PLL. Based on matrix phase detector architecture, a 6.25 GHz PLL achieving 5 GHz BW and exhibiting 55 fs‐rms jitter is designed in 28 nm CMOS bulk technology.