Open AccessPower‐efficient flash ADC with complementary voltage‐to‐time converter
Author(s) -
Oh D.R.,
Jo D.S.,
Moon K.J.,
Roh Y.J.,
Ryu S.T.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.1287
Subject(s) - flash adc , reset (finance) , flash (photography) , voltage , power (physics) , electrical engineering , cmos , electronic engineering , computer science , voltage reference , engineering , physics , optics , quantum mechanics , financial economics , economics
A power‐efficient complementary voltage‐to‐time converter (CVTC) is proposed for a flash ADCs. The alternating reset direction according to the signal development direction reduces the power consumed by the reset operation and the operational frequency of the CVTC is effectively reduced by half. Accordingly, the logic circuits following the CVTC work in a time‐interleaved manner, resulting in significant power saving. A 5‐bit 2.5 GS/s flash ADC designed for a 40 nm CMOS process shows a 27% power reduction over the conventional voltage‐to‐time conversion‐based flash ADC.