Open AccessSelf‐compared bit‐line pairs for eliminating effects of leakage current
Author(s) -
Zhang Jingbo,
Wang Jinkai,
Peng Chunyu,
Li Xuan,
Lin Zhiting,
Wu Xiulong
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.1130
Subject(s) - leakage (economics) , bit (key) , electrical engineering , line (geometry) , electronic engineering , current (fluid) , computer science , engineering , mathematics , computer network , geometry , economics , macroeconomics
This Letter proposes a new scheme to eliminate the bit‐line leakage current of static random access memory. The proposed scheme utilises a four‐input sense amplifier to amplify the voltages of self‐compared bit‐line pairs. The bit‐lines of the proposed structure have no series capacitances and are directly connected to the sense amplifier input. By this way, read delay and error caused by the leakage current of bit‐lines will be eliminated. Simulation results in SMIC 28 nm CMOS process design kits show that the proposed scheme has better stability and can decrease delay time by 41.1% at 0.9 V supply voltage compared with the X‐Calibration technology.