Open Access3T‐2R non‐volatile TCAM with voltage limiter and self‐controlled bias circuit
Author(s) -
Kim C.,
Kwon K.W.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2017.1027
Subject(s) - limiter , voltage , materials science , spice , memory cell , ternary operation , biasing , cmos , electrical engineering , electronic engineering , optoelectronics , computer science , engineering , transistor , programming language
A 3T‐2R non‐volatile ternary content‐addressable‐memory (nvTCAM) is proposed. Using a voltage limiter and self‐controlled bias circuit, both faster match line development and more sensing margin were possible when compared to the conventional nvTCAM. The voltage limiter provides a clear distinction between mismatch cell and ‘don't care’ cell. In case of nvTCAM made of non‐volatile memory (NVM) with a large resistance ratio, the sensing delay is reduced by 43.7% thanks to the combination of the self‐controlled bias circuit and voltage limiter. The proposed circuit works properly with NVM with resistance ratio as low as 3. The proposed nvTCAM cell was evaluated using a 65 nm CMOS process.