Open AccessLow‐power TDC scheme using DLL‐based gray counter for infrared imagers
Author(s) -
Liu Dahe,
Lu Wengao,
Yu Shanzhe,
Chen Zhongjian
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2017.0878
Subject(s) - linearity , cmos , converters , power consumption , electronic engineering , pixel , time to digital converter , electronic circuit , computer science , differential nonlinearity , power (physics) , jitter , electrical engineering , engineering , physics , clock signal , artificial intelligence , quantum mechanics
A low‐power time‐to‐digital converter (TDC) scheme for column‐level single‐slope analogue‐to‐digital converters for infrared imager is presented. This scheme greatly improves the TDC's timing precision with a novel 3‐bit fine gray counter, which makes use of multi‐phase clocks from a delay‐lock‐loop. Aimed for 384 × 288 array size uncooled infrared imager with 17 μm pixel pitch, the TDC circuits have been developed and simulated employing 0.18 μm CMOS technology. Compared with conventional two‐step TDC methods, this method saves more chip area and reduces the sampling power consumption by >50%, and also eliminates the coarse‐fine inconsistency problem with a simulated ±0.1 least‐significant‐bit differential non‐linearity performance.