Open AccessEnhanced aggregation scheduler design in industrial 802.11 devices
Author(s) -
Qian Xu,
Wu Bin,
Ye Tianchun
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.0849
Subject(s) - chipset , computer science , throughput , computer network , overhead (engineering) , scheduling (production processes) , block (permutation group theory) , physical layer , retard , embedded system , wireless , operating system , telecommunications , chip , engineering , psychology , operations management , geometry , mathematics , psychiatry
Industrial WLAN devices suffer from interface delay and poor CPU performance, which would incur an inevitable cost of throughput for aggregation schemes. An enhanced aggregation scheduler is proposed. In this proposed method, the originator's behaviour in both the upper media access control (MAC) and the lower MAC layer is modified. The originator pre‐stores subframes of the next aggregated data units despite that the block Ack is not received. Through utilising the modified method, the hardware delay overhead was minimised. Implementation on own chipset indicates that with this aggregation scheduler, higher throughput can be achieved than conventional scheduler, especially when using high rates.