Open AccessThree‐dimensional AND flash memory
Author(s) -
Kim Y.,
Park I.H.,
Kwon H.T.,
Wee D.,
Park B.G.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2017.0465
Subject(s) - nand gate , flash (photography) , array data structure , stacking , flash memory , computer science , reliability (semiconductor) , erasure , non volatile memory , electronic engineering , electrical engineering , computer hardware , materials science , optoelectronics , logic gate , power (physics) , engineering , physics , optics , algorithm , nuclear magnetic resonance , quantum mechanics , programming language
High‐density and high‐speed charge‐trapping AND flash memory array is fabricated for the first time. A reliability of 10 4 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word‐lines, immunity to back‐pattern dependency, and fast bit‐sensing speed based on a parallel connected cell array structure, which are highly appropriate for three‐dimensional (3D) stacking. Finally, a novel 3D stacked vertical‐AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.