Open AccessReliable NoC design with low latency and power consumption
Author(s) -
Yan Fengxia,
Gao Jianliang
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.4665
Subject(s) - header , router , computer science , network packet , latency (audio) , network on a chip , computer network , embedded system , power consumption , reliability (semiconductor) , low latency (capital markets) , real time computing , power (physics) , telecommunications , physics , quantum mechanics
Reliability has become one of the most crucial issues in network‐on‐chip (NoC). But how to keep low latency and power consumption when achieving reliability is still a curial challenge. A novel scheme for reliable NoCs is proposed. In the scheme, header flit is protected from router to router and data is protected from end to end. To implement the scheme, a new header protection buffer in routers is designed, which can check the timing errors and tolerate the soft errors simultaneously. Instead of checking on each router, data packet is only decoded and checked on receiver's network interface. In this way, the scheme ensures reliable transmission with low latency and power consumption. Experimental results show the feasibility of the proposed scheme in terms of power consumption, latency and area cost.