Open AccessSingle‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process
Author(s) -
Kim E.,
Oh T.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.4290
Subject(s) - cmos , transmitter , data transmission , gigabit , transmission (telecommunications) , electronic engineering , channel (broadcasting) , computer science , chip , electrical engineering , engineering , computer hardware
A smart dual‐mode IO driver and termination scheme is proposed and power is efficiently consumed for both low‐speed data transmission under 500 Mbit/s and high‐speed data transmission up to 3.4 Gbit/s. During high speed data transmission, the driver uses near‐ground signalling and pre‐emphasis weight can be controlled for inter symbol interference (ISI) mitigation. The measured eye shows 17.8% vertically and 19.5% horizontally with finite impulse response (FIR) tap control for 15.75″ FR4 channel. The proto‐type 2 channel single‐ended driver has been implemented in 45 nm CMOS process and occupies 0.022 mm 2 chip area.