Open AccessLow power‐delay‐product dynamic CMOS circuit design techniques
Author(s) -
Xue H.,
Ren S.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.4173
Subject(s) - cmos , power–delay product , electronic engineering , electronic circuit , dynamic demand , benchmark (surveying) , computer science , circuit design , power (physics) , engineering , electrical engineering , adder , physics , geodesy , quantum mechanics , geography
Two low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed techniques can improve circuit PDP by 19.2 and 61.9% in two non‐inverted dynamic benchmarks, respectively, and 6.2 and 33.72% in two inverted dynamic benchmarks, respectively.