Open AccessArea efficient non‐fractional binary‐weighted split‐capacitive‐array DAC for successive‐approximation‐register ADC
Author(s) -
Mao W.,
Li Y.,
Heng C.H.,
Lian Y.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.4043
Subject(s) - shaping , binary number , register (sociolinguistics) , mathematics , successive approximation adc , arithmetic , computer science , electronic engineering , electrical engineering , capacitor , voltage , engineering , linguistics , philosophy
An area efficient non‐fractional binary‐weighted capacitive‐array with attenuation capacitor (NFBWA) digital‐to‐analogue converter (DAC) is presented for successive‐approximation‐register ADC. Based on linearity and matching requirement, the segmentation degrees (i.e. the number of bits in each split capacitive sub‐array) are optimised to minimise the switching power and area. The proposed DAC improves the Walden figure‐of‐merit performance by 1.67 and 5.45 times, respectively, compared with that of fractional binary‐weighted capacitive‐array with attenuation capacitor (FBWA) DAC and conventional NFBWA DAC at the same unit capacitor size and linearity requirement.